codejunkie99
38 verified skills2,169 total stars
gf-release
GateFlow release readiness workflow. Validates plugin manifests, marketplace metadata, docs index coverage, root mirrors, release notes, and component counts before a version tag is created. Use when preparing, checking, or cutting a GateFlow plugin release.
tools76
gf-lint
SystemVerilog lint checker with structured output for orchestration. Runs Verilator lint, categorizes errors/warnings, explains issues, and returns a parseable result block for /gf orchestration.
development63
gf-pcb
KiCad schematic and PCB generation from natural language. AI-verified drafts with DRC/ERC/AI review loop. Example: "design a breakout board for iCE40 with SPI flash and 2 PMODs"
data-ai63
gf-learn-ctx
Contextual learning — micro-lessons embedded in workflow output. Explains hardware concepts on first encounter, tracks what has been taught, generates practice exercises on demand. Used internally by orchestrator — not typically invoked directly.
testing63
gf-sim
SystemVerilog simulator with structured output for orchestration. Auto-detects DUT vs testbench, compiles with Verilator, runs simulation, and returns a parseable result block for /gf orchestration.
development63
gf-plan
Hardware design planner - Creates comprehensive RTL implementation plans. This skill should be used when the user wants to plan a new design, architect a complex feature, or understand how to implement hardware before coding. Example requests: "plan a DMA controller", "design a UART", "architect the memory subsystem"
content-media63
gf-project
Manages .gateflow/project.yaml for project-specific configuration. Auto-detects project settings or prompts user for board, HDL, and target. Used internally by other skills — not typically invoked directly.
testing63
gf-router
Figures out what kind of digital hardware design task the user wants to do, then hands off to the right specialist. Use when the request is unclear, multi-step, or needs help deciding whether to simulate, synthesize, lint, or implement.
development63
gf-viz
Terminal visualization for GateFlow codebase maps. Renders module hierarchies, FSM state diagrams, and module detail cards as interactive ASCII/Unicode art. Example requests: "visualize the codebase", "show hierarchy", "show FSM", "show module detail"
development63
tb-best-practices
Testbench verification best practices and patterns. This skill should be used when the user needs testbench architecture guidance, verification methodology, or wants to write professional-quality testbenches. Example requests: "testbench best practices", "how to structure TB", "verification patterns"
testing63
gf-architect
Codebase architect - Maps and documents SystemVerilog projects. This skill should be used when the user wants to understand a codebase structure, generate architecture documentation, or onboard to a new RTL project. Example requests: "map this codebase", "document the architecture", "show module hierarchy"
development63
gf-learn
SystemVerilog learning mode — generates exercises, reviews solutions, and teaches RTL design patterns. Use when the user wants to learn SystemVerilog, practice hardware design, get exercises, or understand verification methodology.
testing63
gf-pinmap
Board-aware pin mapping. Generates FPGA constraint files (.xdc/.pcf/.lpf/.cst) with correct pin assignments, I/O standards, and drive strength for target boards. Example: "map SPI to PMOD JA on Arty A7", "generate constraints for my iCEBreaker"
data-ai63
gf-pnr
Place and route with nextpnr for open-source FPGA targets. Supports iCE40, ECP5, and Gowin devices. Example: "place and route for iCEBreaker", "run P&R targeting ice40"
development63
gf-protocols
Protocol scaffolding library. Generates correct, readable protocol interface scaffolds (AXI4-Lite, SPI, UART, I2C, AXI4-Full, AXI-Stream, Wishbone) with testbench templates and integration examples. Example: "create an I2C master interface", "scaffold AXI-Stream source"
development63
gf-summary
Summarize Verilator, lint, or simulation output into a readable, actionable format. Use when the user wants to understand build output, lint errors, or simulation results from a Verilator or EDA tool run.
tools63
gf-cocotb
Python-based testbench generation using Cocotb. Alternative to SystemVerilog testbenches for Python-native hardware engineers. Example: "create a cocotb test for the FIFO", "write Python testbench"
development63
gf
Primary SystemVerilog/RTL orchestrator for GateFlow. Routes to specialist agents, runs verification, and iterates until working. Use when the user wants to create, test, fix, or implement any RTL design — FIFO, UART, AXI, state machines, or any digital hardware module.
testing63
gf-build
Parallel build orchestrator for SystemVerilog creation tasks. Decomposes designs into independent modules, builds in parallel phases, runs verification on each component, then integrates. Example: "/gf-build RISC-V CPU with ALU, regfile, decoder, control FSM"
development63
gf-expand
Expand mode - asks clarifying questions, presents options with trade-offs, then hands off to appropriate skill/agent with enriched context.
data-ai63
gf-formal
Formal verification from natural language. Generates SVA properties, configures SymbiYosys, runs proofs, and explains results. Example: "formally verify the FIFO never overflows"
testing63
gf-fusesoc
FuseSoC build system integration for GateFlow. Generates .core files and drives synthesis/simulation through Edalize backends (Vivado, Quartus, open-source tools). Use when the user needs to create a FuseSoC core file, build with Edalize, or integrate RTL into a FuseSoC project.
tools63
gf-ip
IP block library manager. Install, list, and query verified drop-in hardware components. Each block includes RTL, testbench, formal properties, and documentation. Example: "add a FIFO to my project", "/gf-ip add uart"
development63
gf-ip-detect
Auto-detect IP blocks within FPGA and hardware codebases. Scans for module instantiations, identifies missing implementations, matches standard IP patterns, and dispatches agents to fill gaps. Example: "scan for missing IP blocks", "detect what needs implementing", "find unimplemented modules", "auto-fill IP blocks"
development63
gf-plan
Hardware design planner - Creates comprehensive RTL implementation plans. This skill should be used when the user wants to plan a new design, architect a complex feature, or understand how to implement hardware before coding. Example requests: "plan a DMA controller", "design a UART", "architect the memory subsystem"
content-media46
gf-viz
Terminal visualization for GateFlow codebase maps. Renders module hierarchies, FSM state diagrams, and module detail cards as interactive ASCII/Unicode art. Example requests: "visualize the codebase", "show hierarchy", "show FSM", "show module detail"
development46
gf-synth
Synthesize SystemVerilog/Verilog with Yosys. Reports area, timing, and resource utilization. Warns about unsupported SV constructs. Example: "synthesize my design for iCE40"
business46
gf-router
Intent router and expand mode orchestrator for GateFlow. Classifies user intent semantically, determines confidence, triggers expand mode for ambiguous requests, and hands off to appropriate skill/agent.
data-ai46
gf-architect
Codebase architect - Maps and documents SystemVerilog projects. This skill should be used when the user wants to understand a codebase structure, generate architecture documentation, or onboard to a new RTL project. Example requests: "map this codebase", "document the architecture", "show module hierarchy"
development46
gf-lint
SystemVerilog lint checker with structured output for orchestration. Runs Verilator lint, categorizes errors/warnings, explains issues, and returns a parseable result block for /gf orchestration.
development46
gf-build
Parallel build orchestrator for SystemVerilog creation tasks. Decomposes designs into independent modules, builds in parallel phases, runs verification on each component, then integrates. Example: "/gf-build RISC-V CPU with ALU, regfile, decoder, control FSM"
development46
gf-errors
Error translation layer for hardware tool outputs. Converts cryptic Verilator, Yosys, GHDL, and simulation errors into 3-layer explanations. Used internally by gf orchestrator — not user-invocable directly.
tools46
gf-expand
Expand mode - asks clarifying questions, presents options with trade-offs, then hands off to appropriate skill/agent with enriched context.
data-ai46
tb-best-practices
Testbench verification best practices and patterns. This skill should be used when the user needs testbench architecture guidance, verification methodology, or wants to write professional-quality testbenches. Example requests: "testbench best practices", "how to structure TB", "verification patterns"
testing46
gf-summary
Summarize Verilator/lint output in a readable format
development46
skills/gf
--- name: gf description: Primary SystemVerilog orchestrator. Handles all RTL tasks end-to-end - routes to agents, runs verification, iterates until working. Examples: "create a FIFO", "test my UART", "fix lint errors", "implement and verify" allowed-tools: - Grep - Glob - Read - Write - Edit - Bash - Task - WebFetch - AskUserQuestion - Skill --- # GF - SystemVerilog Development Orchestrator You are the primary entry point for all SystemVerilog development. Your job is to *
tools46
gf-sim
SystemVerilog simulator with structured output for orchestration. Auto-detects DUT vs testbench, compiles with Verilator, runs simulation, and returns a parseable result block for /gf orchestration.
development46
gf-learn
SystemVerilog learning mode - generates exercises, reviews solutions
testing46