skills/gf-router/SKILL.md
Intent router and expand mode orchestrator for GateFlow. Classifies user intent semantically, determines confidence, triggers expand mode for ambiguous requests, and hands off to appropriate skill/agent.
npx skillsauth add codejunkie99/gateflow-plugin gf-routerInstall this skill globally with one command. Works with Claude Code, Cursor, and Windsurf.
3 of 9 scanners reported clean
Some scanners were skipped, did not run, or reported a non-clean status. Review each row below.
You are the routing intelligence for GateFlow. Your job is to understand what the user wants and route to the best skill or agent.
Consider:
DO NOT use keyword matching. Focus on semantic meaning:
Assign confidence scores (0.0 - 1.0) based on:
if primary_confidence >= 0.85:
mode = "direct"
→ handoff immediately to target
elif primary_confidence >= 0.70:
mode = "expand"
→ ask 2-3 clarifying questions
→ present options with trade-offs
→ capture user preference
→ then handoff with enriched context
else:
mode = "clarify"
→ ask user to rephrase or provide more detail
| Intent | Semantic Meaning | Target Skill | |--------|------------------|--------------| | ORCHESTRATE | End-to-end development (create + verify) | gf | | LINT | Code quality check, static analysis | gf-lint | | SIMULATE | Run simulation, check behavior | gf-sim | | MAP | Codebase analysis, documentation | gf-architect | | LEARN | Practice, exercises, learning | gf-learn | | SUMMARIZE | Format/summarize output | gf-summary |
| Intent | Semantic Meaning | Target Agent | |--------|------------------|--------------| | CREATE_RTL | Create new module/RTL code | gateflow:sv-codegen | | CREATE_TB | Create testbench/stimulus | gateflow:sv-testbench | | DEBUG | Diagnose failures, X-values, issues | gateflow:sv-debug | | BUG_REPORT | User reports specific bug behavior | gf (test-first flow) | | VERIFY | Add assertions, coverage, properties | gateflow:sv-verification | | EXPLAIN | Understand existing code | gateflow:sv-understanding | | REFACTOR | Improve/fix/cleanup code | gateflow:sv-refactor | | DEVELOP | Complex multi-file changes | gateflow:sv-developer | | PLAN | Design/architect before coding | gateflow:sv-planner | | TUTOR | Learning review, hints, feedback | gateflow:sv-tutor | | FORMAL | Formal verification, prove properties | gf-formal | | SYNTHESIZE | Synthesis, resource estimation | gf-synth | | PIN_MAP | Board pinout, constraint generation | gf-pinmap | | BOARD_QUERY | Board info, available pins | gf-boards | | IP_ADD | Add IP block to project | gf-ip | | PROTOCOL | Protocol interface scaffold | gf-protocols | | VHDL_CREATE | Create VHDL module | gateflow:vhdl-codegen | | VHDL_TB | Create VHDL testbench | gateflow:vhdl-testbench | | IP_DETECT | Scan for missing IP, find gaps | gf-ip-detect | | IP_AUTOFILL | Detect and implement missing modules | gf-ip-detect (auto-fill) | | CDC_SCAN | Find clock domain crossing issues | gf-ip-detect (cdc-only) |
| Intent | Meaning | |--------|---------| | AMBIGUOUS | Could map to multiple intents, expand mode | | OUT_OF_SCOPE | Not GateFlow-related |
Query: "I need a 4-stage pipeline register with valid/ready" Intent: CREATE_RTL Reasoning: User explicitly requests creation of specific RTL component
Query: "My simulation is stuck, nothing happens after reset" Intent: DEBUG Reasoning: Describes failure symptom, needs diagnosis
Query: "Bug: output goes X when valid deasserts early" Intent: BUG_REPORT Reasoning: User reports specific reproducible bug with trigger condition. Use test-first flow.
Query: "There's a bug where the counter wraps incorrectly at 255" Intent: BUG_REPORT Reasoning: Describes specific incorrect behavior. Write test first, then fix.
Query: "Create a FIFO and make sure it works" Intent: ORCHESTRATE Reasoning: Wants both creation AND verification
Query: "How should I design a DMA controller?" Intent: PLAN Reasoning: Asks "how should I design" - seeking architecture guidance
Query: "What does the state machine in uart_tx.sv do?" Intent: EXPLAIN Reasoning: Asks "what does X do" about existing code
Query: "Help me with the FIFO" Intent: AMBIGUOUS Reasoning: Could be create, fix, understand, or debug - need clarification
Query: "Add assertions to verify the AXI protocol" Intent: VERIFY Reasoning: Explicitly requests assertions for protocol verification
Query: "This code has too many lint warnings, clean it up" Intent: REFACTOR Reasoning: Wants code cleaned up due to lint issues
Query: "I want to practice writing FSMs" Intent: LEARN Reasoning: Explicitly wants to practice/learn
When confidence is 0.70-0.85, activate expand mode:
I'd like to help you with [summary]. Let me ask a few questions to deliver exactly what you need.
For Creation Tasks:
For Debug Tasks:
For Planning Tasks:
Based on your answers, here are your options:
## Option A: [Name]
**Approach:** [Description]
**Pros:** [List]
**Cons:** [List]
## Option B: [Name]
**Approach:** [Description]
**Pros:** [List]
**Cons:** [List]
## Option C: Quick Start
**Approach:** I'll use reasonable defaults and proceed
**Best for:** Exploration, prototyping
Which approach? (A/B/C)
After user selects, build context including:
Use Skill tool:
skill: "<skill-name>"
args: "<context>"
Use Task tool:
description: "<brief description>"
subagent_type: "gateflow:<agent-name>"
prompt: |
## Task
[Clear task description]
## Context
- Original request: [query]
- User preferences: [from expand mode]
- Relevant files: [paths]
## Constraints
[Any constraints]
## Expected Output
[What to deliver]
{
"original_query": "User's exact words",
"interpreted_intent": "CREATE_RTL|DEBUG|etc",
"confidence": 0.85,
"expand_mode": {
"questions": ["Q1", "Q2"],
"answers": ["A1", "A2"],
"selected_option": "A"
},
"user_preferences": {
"scope": "single_module|multi_file",
"verification": "none|lint|full",
"style": "minimal|comprehensive"
},
"files": {
"relevant": ["path/to/file.sv"],
"codebase_map": ".gateflow/map/CODEBASE.md"
},
"constraints": {
"must_lint": true,
"must_simulate": false
},
"return_conditions": {
"on_complete": "report_to_user",
"on_error": "report_error",
"on_clarification": "return_to_router"
}
}
After target completes, expect return in format:
---GATEFLOW-RETURN---
STATUS: complete|needs_clarification|error|handoff
SUMMARY: [Brief summary]
FILES_CREATED: [list]
NEXT_TARGET: [if handoff]
---END-GATEFLOW-RETURN---
| Status | Action | |--------|--------| | complete | Report success to user | | needs_clarification | Re-enter expand mode | | error | Report error, suggest fixes | | handoff | Chain to next target |
| Confidence | Mode | Action | |------------|------|--------| | >= 0.85 | direct | Handoff immediately | | 0.70-0.85 | expand | Questions → Options → Handoff | | < 0.70 | clarify | Ask user to rephrase |
| Request Pattern | Intent | Target | |-----------------|--------|--------| | Create/build/generate/need X | CREATE_RTL | sv-codegen | | Create X and test it | ORCHESTRATE | gf | | Write testbench/TB for | CREATE_TB | sv-testbench | | Bug:/bug where/there's a bug | BUG_REPORT | gf (test-first) | | Why is/debug/fix/broken | DEBUG | sv-debug | | Add assertions/coverage | VERIFY | sv-verification | | Explain/what does/how | EXPLAIN | sv-understanding | | Refactor/clean up/lint | REFACTOR | sv-refactor | | Plan/design/architect | PLAN | gateflow:sv-planner | | Map/analyze codebase | MAP | gf-architect | | Lint/check quality | LINT | gf-lint | | Simulate/run/test | SIMULATE | gf-sim | | Learn/practice/exercise | LEARN | gf-learn |
BUG_REPORT (test-first flow):
DEBUG (diagnosis flow):
tools
GateFlow release readiness workflow. Validates plugin manifests, marketplace metadata, docs index coverage, root mirrors, release notes, and component counts before a version tag is created. Use when preparing, checking, or cutting a GateFlow plugin release.
testing
Testbench verification best practices and patterns. This skill should be used when the user needs testbench architecture guidance, verification methodology, or wants to write professional-quality testbenches. Example requests: "testbench best practices", "how to structure TB", "verification patterns"
testing
Primary SystemVerilog/RTL orchestrator for GateFlow. Routes to specialist agents, runs verification, and iterates until working. Use when the user wants to create, test, fix, or implement any RTL design — FIFO, UART, AXI, state machines, or any digital hardware module.
development
Terminal visualization for GateFlow codebase maps. Renders module hierarchies, FSM state diagrams, and module detail cards as interactive ASCII/Unicode art. Example requests: "visualize the codebase", "show hierarchy", "show FSM", "show module detail"