.claude/skills/domain-layer/SKILL.md
Instructions for electronics-specific logic and build processes: netlists, PCBs, build steps, and exporters. Use when implementing or modifying build steps, exporters, PCB generation, or BOM/netlist output.
npx skillsauth add atopile/atopile domain-layerInstall this skill globally with one command. Works with Claude Code, Cursor, and Windsurf.
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The domain layer (primarily src/atopile/build_steps.py and src/faebryk/exporters/) encompasses the logic and processes specific to electronic hardware engineering. This includes the build pipeline that transforms a compiled graph into manufacturing artifacts (Gerbers, BOMs, Pick & Place).
Run the standard build pipeline from a project directory (where ato.yaml lives):
ato build
src/atopile/build_steps.py
Muster class (a DAG-based task runner).generate_bom, generate_manufacturing_data, update_pcb, etc.src/atopile/build.py (constructs app graph from .ato or .py, runs unit inference)src/faebryk/exporters/
layout_sync.py).jlcpcb.py, etc.).src/atopile/layout.py (generates .layouts.json module→layout mapping)src/atopile/kicad_plugin/README.md (plugin workflow overview)src/atopile/cli/build.py): The ato build command directly invokes build_steps.muster to execute the pipeline.generate_3d_render).generate_bom depends on build_design).update_pcb).atopile.config (not covered here, but relevant).src/faebryk/exporters/ and register a wrapper function in build_steps.py using @muster.register.test/end_to_end/ or test/integration/.ato build on a sample project and inspect the generated artifacts (Gerbers, BOM csv).ato dev test --llm test/test_muster.py -qvirtual=True for targets that just group other targets (e.g. all or default).update_pcb or layout_sync logic to avoid dataloss of user's manual PCB routing.development
How the Faebryk parameter solver works (Sets/Literals, Parameters, Expressions), the core invariants enforced during mutation, and practical workflows for debugging and extending the solver. Use when implementing or modifying constraint solving, parameter bounds, or debugging expression simplification.
development
# SEXP Benchmark Strategy ## Goal Measure and improve S-expression pipeline performance with a focus on: - Throughput per stage - Peak memory per stage - End-to-end behavior on realistic KiCad PCB inputs ## Pipeline Stages Benchmark these layers separately: - `tokenizer` - `ast` - `parser` (typed decode) - `encode` (typed encode to raw SEXP) - `pretty` (formatting) ## Dataset Dimensions Use a matrix over: - `depth`: shallow vs deep nesting - `size`: small, medium, large Recommended size buck
development
How the Zig S-expression engine and typed KiCad models work, how they are exposed to Python (pyzig_sexp), and the invariants around parsing, formatting, and freeing. Use when working with KiCad file parsing, S-expression generation, or layout sync.
tools
How the Zig↔Python binding layer works (pyzig), including build-on-import, wrapper generation patterns, ownership rules, and where to add new exported APIs. Use when adding Zig-Python bindings, modifying native extensions, or debugging C-API interactions.