skills/jlcpcb/SKILL.md
JLCPCB PCB fabrication and assembly — BOM/CPL generation, basic vs extended parts, assembly constraints, design rules, ordering workflow. Use with KiCad for JLCPCB manufacturing. Use this skill when the user mentions JLCPCB, wants to order PCBs or assembled boards, needs prototype bare PCBs and stencils, wants to know JLCPCB design rules and capabilities, or is asking about PCB manufacturing costs or turnaround times. For gerber/CPL export, stencil ordering, and BOM management, see the `bom` skill.
npx skillsauth add aklofas/kicad-happy jlcpcbInstall this skill globally with one command. Works with Claude Code, Cursor, and Windsurf.
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JLCPCB is a PCB fabrication and assembly service based in Shenzhen, China. It is a sister company to LCSC Electronics (common ownership) — they share the same parts library.
Typical usage: Order bare prototype PCBs + framed stencil from JLCPCB during prototyping (parts sourced separately from DigiKey/Mouser, hand-assembled in lab). For production runs (100s qty), order fully assembled boards from JLCPCB using LCSC parts. PCBWay is an alternative assembler. For component searching, see the lcsc skill. For BOM management, gerber/CPL export, and stencil ordering, see the bom skill.
| Skill | Purpose |
|-------|---------|
| kicad | Read/analyze KiCad project files, DFM scoring against JLCPCB capabilities |
| bom | BOM management, gerber/CPL export, stencil ordering |
| digikey | Search DigiKey (prototype sourcing, primary — also preferred for datasheet downloads via API) |
| mouser | Search Mouser (prototype sourcing, secondary) |
| lcsc | Search LCSC (production sourcing — JLCPCB uses LCSC parts library) |
| pcbway | Alternative PCB fabrication & assembly |
| emc | EMC pre-compliance risk analysis — run before fab to catch EMC issues |
| spice | SPICE simulation — verify analog subcircuits before committing to fab |
| Category | Description | Assembly Fee | |----------|-------------|--------------| | Basic | ~698 common parts (resistors, caps, diodes, etc.) pre-loaded on pick-and-place machines | No extra fee | | Preferred Extended | Frequently used extended parts | No feeder loading fee (Economic assembly) | | Extended | 300k+ less common parts loaded on demand | $3 per unique extended part |
Every assembly component is identified by an LCSC Part Number (Cxxxxx, e.g., C14663). This is the definitive identifier for BOM matching. See the lcsc skill for searching parts.
https://jlcpcb.com/parts/componentSearch?searchTxt=<query>https://jlcpcb.com/parts/basic_partsJLCPCB accepts CSV, XLS, or XLSX BOMs with these columns:
| Column | Required | Description |
|--------|----------|-------------|
| Comment / Value | Yes | Component value (e.g., 100nF, 10k) |
| Designator | Yes | Reference designators, comma-separated (e.g., C1,C2,C5) |
| Footprint | Yes | Package/footprint name |
| LCSC Part # | Recommended | LCSC part number (Cxxxxx) — guarantees exact match |
The column header for LCSC numbers must be exactly "LCSC Part #" or "LCSC Part Number" — typos cause upload failures.
LCSC field to each symbol with the LCSC part numberReference -> DesignatorValue -> CommentFootprint -> FootprintLCSC -> LCSC Part #For gerber export settings, CPL format, and stencil ordering, see the bom skill.
Apply at https://api.jlcpcb.com. Access is gated — requires review based on order history and business profile.
Available APIs (once approved):
| Parameter | Minimum | |-----------|---------| | Trace width | 0.127mm (5mil) | | Trace spacing | 0.127mm (5mil) | | Via diameter | 0.45mm | | Via drill | 0.2mm | | Annular ring | 0.125mm | | Min hole size | 0.2mm | | Board thickness | 0.4-2.4mm (default 1.6mm) | | Min board size | 6x6mm | | Max board size | 500x400mm (2-layer) |
| Parameter | Minimum | |-----------|---------| | Trace width | 0.09mm (3.5mil) | | Trace spacing | 0.09mm (3.5mil) | | Via diameter | 0.25mm | | Via drill | 0.15mm | | Board thickness | 0.6-2.4mm |
If you have a JLCPCB .kicad_dru design rules file, import it in KiCad Board Editor > Board Setup > Design Rules > Import Settings.
| Feature | Economic | Standard | |---------|----------|----------| | Sides | Top only | Top + Bottom | | Component types | SMD only | SMD + through-hole | | Min component size | 0201 | 01005 | | Fine-pitch BGA/QFP | Down to 0.5mm pitch | Down to 0.4mm pitch | | Turnaround | ~3-5 days | ~3-5 days | | Extended part fee | $3 per unique part | $3 per unique part |
JLCPCB's pick-and-place uses different rotation conventions than KiCad for some footprints. Common offsets:
| Footprint Family | Typical Offset | |-----------------|----------------| | SOT-23, SOT-23-5, SOT-23-6 | +180° | | SOT-223 | +180° | | SOIC-8, SOIC-16 | +90° or +270° | | QFN (all sizes) | +90° | | SMA/SMB/SMC diodes | +180° | | USB-C connectors | Varies — check datasheet |
To fix rotation issues:
bom skill for export settings)https://cart.jlcpcb.com/quote — configure layers, thickness, color, qtybom skill for export settings)bom skill for format)https://cart.jlcpcb.com/quote — configure layers, thickness, color, qtylcsc skill to searchdocumentation
Generate professional engineering documentation from KiCad projects — Hardware Design Descriptions (HDD), CE Technical Files, Interface Control Documents (ICD), Design Review Packages, and Manufacturing Transfer Packages. Auto-runs schematic, PCB, EMC, and thermal analyses; renders schematic and PCB SVGs with subsystem cropping, focus dimming, net highlighting, and pin-net annotation; generates power tree, bus topology, and architecture block diagrams. Produces styled PDF with cover pages, TOC, and vector SVG embedding. Markdown source of truth — human-editable, version-controllable. Use for "generate documentation", "create report", "HDD", "CE technical file", "design review package", "ICD", "render schematic", "render layout", "generate block diagram", "manufacturing package", "generate PDF", or "custom report".
development
EMC pre-compliance risk analysis for KiCad PCB designs — 17 check categories, 42 rule IDs covering ground planes, decoupling, I/O filtering, switching harmonics, clock routing, differential pair skew, board edge radiation, PDN impedance, return paths, crosstalk, ESD protection, and shielding. Produces severity-ranked risk report with pre-compliance test plan. Supports FCC Part 15, CISPR 32, CISPR 25 (automotive), MIL-STD-461G. SPICE-enhanced when available. Use when the user asks about EMC, EMI, radiated/conducted emissions, FCC compliance, CE marking, CISPR, ground plane issues, decoupling strategy, clock routing EMC, switching noise, differential pair skew, or whether their board will pass EMC testing. Also for "will this pass FCC?", "check my EMC", "is my ground plane okay?", "check my decoupling", or "generate an EMC test plan".
testing
Run automatic SPICE simulations on subcircuits detected from KiCad schematic analysis — validates filter frequencies, divider ratios, opamp gains, LC resonance, and crystal load capacitance. Supports ngspice, LTspice, and Xyce (auto-detected). Generates testbenches, runs batch mode, produces structured pass/warn/fail report. Use when the user asks to simulate, verify, or validate any analog subcircuit — RC filters, LC filters, voltage dividers, opamp circuits, crystal oscillators. Also for "simulate my circuit", "run spice", "verify with simulation", "check my filter cutoff", "does this divider give the right voltage", "what's the bandwidth of this opamp stage". Consider suggesting simulation during design reviews when the schematic analyzer reports simulatable subcircuits and a SPICE simulator is available.
development
Analyze KiCad projects and PDF schematics: schematics, PCB layouts, Gerbers, footprints, symbols, netlists, and design rules. Reviews designs for bugs, traces nets, cross-references schematic to PCB, extracts BOM data, checks DRC/ERC, DFM, power trees, and regulator circuits. Analyzes PDF schematics from dev boards, reference designs, eval kits, and datasheets. Supports KiCad 5–10. Use whenever the user mentions .kicad_sch, .kicad_pcb, .kicad_pro, PCB design review, schematic analysis, PDF schematics, reference designs, Gerber files, DRC/ERC, netlist issues, BOM extraction, signal tracing, power budget, DFM, or wants to understand, debug, compare, or review any hardware design. Also for "check my board", "review before fab", "what's wrong with my schematic", "is this ready to order", "check my power supply", "verify this circuit", or any electronics/PCB design question.