skills/kidoc/SKILL.md
Generate professional engineering documentation from KiCad projects — Hardware Design Descriptions (HDD), CE Technical Files, Interface Control Documents (ICD), Design Review Packages, and Manufacturing Transfer Packages. Auto-runs schematic, PCB, EMC, and thermal analyses; renders schematic and PCB SVGs with subsystem cropping, focus dimming, net highlighting, and pin-net annotation; generates power tree, bus topology, and architecture block diagrams. Produces styled PDF with cover pages, TOC, and vector SVG embedding. Markdown source of truth — human-editable, version-controllable. Use for "generate documentation", "create report", "HDD", "CE technical file", "design review package", "ICD", "render schematic", "render layout", "generate block diagram", "manufacturing package", "generate PDF", or "custom report".
npx skillsauth add aklofas/kicad-happy kidocInstall this skill globally with one command. Works with Claude Code, Cursor, and Windsurf.
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Generate professional engineering documentation from KiCad project files.
One command generates the full scaffold — analyses, diagrams, renders, and markdown are all produced automatically:
python3 skills/kidoc/scripts/kidoc_scaffold.py \
--project-dir /path/to/kicad/project \
--type hdd \
--output reports/HDD.md
This auto-detects .kicad_sch and .kicad_pcb files, runs schematic/PCB/EMC/thermal analyses, generates block diagrams and schematic SVG renders, and produces a structured markdown scaffold with pre-filled data tables and narrative placeholders.
To produce a PDF:
python3 skills/kidoc/scripts/kidoc_generate.py \
--project-dir /path/to/kicad/project \
--doc reports/HDD.md \
--format pdf
Creates reports/.venv/ automatically on first run (PDF/DOCX/ODT only — HTML is zero-dep).
kidoc_scaffold.py auto-runs all available analyses, renders schematics, generates diagrams, and writes the markdown scaffold.<!-- NARRATIVE: section_name --> placeholder. The engineer reviews and edits.<!-- GENERATED: section_id --> markers update from fresh analysis; user-written narrative content is preserved.kidoc_generate.py produces PDF, HTML, DOCX, or ODT.| Type | Name | Key Sections |
|------|------|-------------|
| hdd | Hardware Design Description | System overview, power, signals, analog, thermal, EMC, PCB, mechanical, BOM, test, compliance |
| ce_technical_file | CE Technical File | Product ID, essential requirements, harmonized standards, risk assessment, Declaration of Conformity |
| design_review | Design Review Package | Review summary (cross-analyzer scores), findings, action items |
| icd | Interface Control Document | Interface list, per-connector pinout details, electrical characteristics |
| manufacturing | Manufacturing Transfer Package | Assembly overview, PCB fab notes, assembly instructions, test procedures |
| schematic_review | Schematic Review Report | System overview, power, signals, analog, BOM, schematic appendix |
| power_analysis | Power Analysis Report | Power design, thermal, EMC, BOM |
| emc_report | EMC Pre-Compliance Report | EMC analysis, compliance, schematic appendix |
Use --spec to generate reports with arbitrary section ordering:
python3 skills/kidoc/scripts/kidoc_scaffold.py \
--project-dir . --spec my-report.json --output reports/custom.md
Spec format (JSON):
{
"type": "custom",
"title": "USB Interface Analysis",
"sections": [
{"id": "front_matter", "type": "front_matter"},
{"id": "signal_interfaces", "type": "signal_interfaces"},
{"id": "bom", "type": "bom_summary"}
]
}
Each section's type must match a known section type (same names used in the document types table above). The id field is a unique key for that section instance.
To see the full default spec for any built-in type:
python3 skills/kidoc/scripts/kidoc_spec.py --expand hdd
python3 skills/kidoc/scripts/kidoc_spec.py --list
The --spec flag also works with kidoc_generate.py (uses the spec title as fallback project name).
Rendering is integrated into the figure generation engine. The orchestrator and scaffold automatically render schematics and PCB views as part of document generation:
# Generate all figures (diagrams + schematic/PCB renders) from analysis JSON
python3 skills/kidoc/scripts/kidoc_diagrams.py --analysis schematic.json --output reports/figures/
# Full orchestration with spec, analysis, and project files
python3 skills/kidoc/scripts/kidoc_orchestrator.py --analysis schematic.json \
--project-dir . --output reports/figures/
The figure generators support: full-sheet rendering (root + all sub-sheets), subsystem cropping (focus_refs in spec sections), net highlighting, pin-level net annotation, and all PCB layer presets. These options are configured in the document spec or passed through the analysis dict.
Rendering features available through the generator framework:
For direct programmatic access, use figures.renderers:
from figures.renderers import render_schematic, render_pcb
render_schematic('design.kicad_sch', 'output/', crop_refs=['R1', 'R2'], highlight_nets=['VCC'])
render_pcb('board.kicad_pcb', 'output/', preset_name='assembly-front')
Layer presets:
| Preset | Shows |
|--------|-------|
| assembly-front | Front silk, fab, pads, outline |
| assembly-back | Back silk, fab, pads, outline (mirrored) |
| routing-front | Front copper, pads, vias, outline |
| routing-back | Back copper, pads, vias, outline |
| routing-all | All copper layers, pads, vias, zones |
| power | Power planes, vias, zone outlines |
Additional options: --highlight-nets, --crop-refs, --crop x,y,w,h, --mirror, --overlay annotations.json (callout boxes with leader lines).
python3 skills/kidoc/scripts/kidoc_diagrams.py --analysis schematic.json --all --output diagrams/
python3 skills/kidoc/scripts/kidoc_diagrams.py --analysis schematic.json --power-tree --output diagrams/
python3 skills/kidoc/scripts/kidoc_diagrams.py --analysis schematic.json --bus-topology --output diagrams/
python3 skills/kidoc/scripts/kidoc_diagrams.py --analysis schematic.json --architecture --output diagrams/
Generated from schematic analysis JSON. Power trees show regulator topology with inductor values, capacitor summaries, and output voltages.
| Format | SVG Handling | Dependencies |
|--------|-------------|------|
| Markdown | Image references | Zero-dep |
| HTML | Inlined as vector | Zero-dep |
| PDF | Vector via svglib, custom converter fallback, raster fallback | Venv (reports/.venv/) |
| DOCX | Rasterized to 300 DPI PNG | Venv |
| ODT | Rasterized to 300 DPI PNG | Venv |
PDF output includes a styled cover page, table of contents, formatted tables with alternating rows, and vector SVG diagrams.
Report settings live in .kicad-happy.json under the "reports" key. Config files cascade: ~/.kicad-happy.json (user-level defaults, e.g. company branding) merges with project-level config.
{
"project": {
"name": "Widget Board",
"number": "HW-2024-042",
"revision": "1.2",
"company": "Acme Electronics",
"author": "Jane Smith",
"market": "eu"
},
"reports": {
"classification": "Company Confidential",
"documents": [
{"type": "hdd", "output": "HDD-{project}-{rev}", "formats": ["pdf", "docx"]}
],
"branding": {
"logo": "templates/logo.png",
"header_left": "{company}",
"header_right": "{number} Rev {rev}"
}
}
}
After generating a scaffold, fill the narrative placeholder sections with engineering prose.
Run the context builder to get focused data for each section:
python3 skills/kidoc/scripts/kidoc_narrative.py \
--analysis analysis/schematic.json \
--section power_design
Or build contexts for all narrative sections at once:
python3 skills/kidoc/scripts/kidoc_narrative.py \
--analysis analysis/schematic.json \
--report reports/HDD.md
For each section, read the context and write prose that:
Replace the italic placeholder *[...]* in the markdown with real prose.
On regeneration, data tables update automatically. Review narratives for consistency with any changed data.
Write as a senior EE explaining to a peer:
python3-venv (for PDF/DOCX/ODT generation).kicad_sch, KiCad 6+) — for SVG rendering.kicad_sch/.kicad_pcb; pre-generated JSONs in analysis/ (or the path configured in .kicad-happy.json) are used if present. Generated figures (diagrams, schematic SVGs) are placed in reports/figures/ for git tracking.kicad_sch, .kicad_pcb)| Skill | Relationship |
|-------|-------------|
| kicad | Produces schematic/PCB/thermal analysis JSON consumed by scaffolds |
| emc | Produces EMC analysis JSON for EMC sections |
| spice | SPICE simulation results appear in analog design sections |
| bom | BOM data appears in BOM summary sections |
Run the kicad skill's analyzers first, then emc and spice if available. The scaffold auto-runs kicad and emc analyses when source files are present, so manual pre-analysis is only needed for SPICE.
development
EMC pre-compliance risk analysis for KiCad PCB designs — 17 check categories, 42 rule IDs covering ground planes, decoupling, I/O filtering, switching harmonics, clock routing, differential pair skew, board edge radiation, PDN impedance, return paths, crosstalk, ESD protection, and shielding. Produces severity-ranked risk report with pre-compliance test plan. Supports FCC Part 15, CISPR 32, CISPR 25 (automotive), MIL-STD-461G. SPICE-enhanced when available. Use when the user asks about EMC, EMI, radiated/conducted emissions, FCC compliance, CE marking, CISPR, ground plane issues, decoupling strategy, clock routing EMC, switching noise, differential pair skew, or whether their board will pass EMC testing. Also for "will this pass FCC?", "check my EMC", "is my ground plane okay?", "check my decoupling", or "generate an EMC test plan".
testing
Run automatic SPICE simulations on subcircuits detected from KiCad schematic analysis — validates filter frequencies, divider ratios, opamp gains, LC resonance, and crystal load capacitance. Supports ngspice, LTspice, and Xyce (auto-detected). Generates testbenches, runs batch mode, produces structured pass/warn/fail report. Use when the user asks to simulate, verify, or validate any analog subcircuit — RC filters, LC filters, voltage dividers, opamp circuits, crystal oscillators. Also for "simulate my circuit", "run spice", "verify with simulation", "check my filter cutoff", "does this divider give the right voltage", "what's the bandwidth of this opamp stage". Consider suggesting simulation during design reviews when the schematic analyzer reports simulatable subcircuits and a SPICE simulator is available.
development
Analyze KiCad projects and PDF schematics: schematics, PCB layouts, Gerbers, footprints, symbols, netlists, and design rules. Reviews designs for bugs, traces nets, cross-references schematic to PCB, extracts BOM data, checks DRC/ERC, DFM, power trees, and regulator circuits. Analyzes PDF schematics from dev boards, reference designs, eval kits, and datasheets. Supports KiCad 5–10. Use whenever the user mentions .kicad_sch, .kicad_pcb, .kicad_pro, PCB design review, schematic analysis, PDF schematics, reference designs, Gerber files, DRC/ERC, netlist issues, BOM extraction, signal tracing, power budget, DFM, or wants to understand, debug, compare, or review any hardware design. Also for "check my board", "review before fab", "what's wrong with my schematic", "is this ready to order", "check my power supply", "verify this circuit", or any electronics/PCB design question.
testing
PCBWay PCB fabrication and assembly — turnkey/consigned assembly, design rules, ordering workflow. Alternative to JLCPCB for manufacturing. Use with KiCad. Use this skill when the user mentions PCBWay, needs turnkey assembly (PCBWay sources parts by MPN), has parts not available on LCSC, needs assembled boards with non-LCSC components, wants to compare PCBWay vs JLCPCB, or needs assembly with parts sourced globally rather than from LCSC only. For gerber/CPL export, stencil ordering, and BOM management, see the `bom` skill.