ShaneLogic/cdte-cell-degradation-analysis

CdTe Cell Degradation Analysis

When to Use

• Evaluating CdS/CdTe cell stability under stress conditions
• Diagnosing unexpected Voc loss in CdTe cells
• Analyzing back contact degradation issues
• Planning accelerated lifetime testing protocols
• Investigating copper-related degradation in back contacts

Degradation Assessment

Normal Operating Conditions

CdS/CdTe cells are relatively stable under:

• Normal day/night outdoor cycles
• Operation near maximum power point
• Standard operating temperatures

Stress-Induced Degradation

Trigger conditions:

• Constant full illumination (AM1) at elevated temperatures
• Open circuit voltage condition (worst case)

Symptoms:

• Substantial decrease in open circuit voltage (Voc)
• ~80mV Voc loss per month at 100°C, AM1, open circuit
• I-V curve bending at higher bias
• Reduced rectification in dark characteristics
• Dark current shifts to higher values

Degradation Location

Primary site: Back contact region

• Evidence: Dark current degradation, diode effect reduction
• Mechanism: Copper diffusion/migration likely cause

Recovery Procedures

Recovery Conditions

1. Return cell to short circuit load
2. Store in dark conditions
3. Duration: Few days for nearly full recovery

Recontacting (Partial Recovery)

If recovery is insufficient:

1. Etch off back electrode
2. Apply new back contact
3. Result: Partial restoration of characteristics
4. Note: Some Voc degradation may persist permanently

Back Contact Optimization

Copper Thickness Guidelines

• Dark characteristics: Need ≥15nm Cu for reasonable initial diode behavior
• Illuminated characteristics: ≥2nm Cu sufficient
• Trade-off: Thicker Cu may accelerate degradation

Processing Methods

• Dry (evaporation) vs. wet (etching) processing affects degradation rates
• Optimize for target lifetime requirements

Production Stability Targets

• Large panels (>1 m²): Edge-to-edge efficiencies >10%
• Life expectancy: >10 years at >80% initial performance