jitx-code-review/SKILL.md
Same-model self-critique pass for JITX Python code just written in this workspace. Use when the user asks to "review my JITX code", "self-critique", "check JITX conventions", "find string-hacking", "check framework-boundary issues", "audit before merge", or any equivalent. Mandatory for complete-board tier at task acceptance (folds into Think Twice); user-invoked for single-task work. Catches the architectural failure modes that grep gates and static linters miss — parallel string-keyed models, reflection-as-iteration (regardless of whether on self), owner-shaped data misplaced in design code, build-spec-then-iterate, module-import-time parallel models, and framework-boundary-bypass (the "framework does it, therefore so can I" trap). Applies an ownership test to every banned-pattern hit or proposed exception. Produces severity-tagged findings (CRITICAL / WARNING / NOTE) that fold into the task acceptance block.
npx skillsauth add jitx-inc/jitx-skills jitx-code-reviewInstall this skill globally with one command. Works with Claude Code, Cursor, and Windsurf.
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Task-level architectural self-review for JITX Python code just written in the current workspace. The reviewer agent reads the code with a checklist-bound, evidence-anchored framing — different from the framing under which the code was written — which is what catches what the in-session author rationalized as fine.
This skill is the per-task same-model pre-pass in the Think Twice flow (see jitx/references/task-execution.md Part A Step 4 and jitx/references/outside-voice-review.md "Same-model passes precede codex"). It catches architectural and code-craft smells (string-hacking, parallel models, naming hygiene). Codex outside-voice — which runs only for trigger-list task classes (MCU/FPGA, RF, power, safety, high-speed digital, battery) — catches the JITX-engineering-domain issues (datasheet-vs-code, impedance/return-path, voltage-divider math).
Phase 3b's same-model pre-pass is the four-pass design audit (not this skill) — see jitx/references/completion-blocks.md "Phase 3b Design Audit Block". By the time Phase 3b runs, every Phase 1/2/3 task has already passed its per-task jitx-code-review and the findings live in the task acceptance blocks.
jitx base skill invokes this at the Think Twice step in task-execution.md Part A Step 4 (before the orchestrator's acceptance review). The task acceptance block's JITX code review (self): field carries the finding count + disposition; missing or not run defaults to block.jitx/references/outside-voice-review.md).<ns>/ directory (everything just written for the current task). The orchestrator may scope tighter (single file) when invoking from Think Twice.jitx/SKILL.md Don'ts (always)jitx/references/architectural-patterns.md (always — this is the worked-counter-example source for the dominant failure modes)jitx-code-review/references/checklist.md (the pattern index over the architecture doctrine)The review is evidence-anchored: every finding cites file:line and quotes a rule sentence (from SKILL.md or a reference file). Findings without a citation are downgraded to NOTE.
<ns>/, but a scoped run can target a single file.references/checklist.md). For each pattern, look for instances; for each instance, capture severity and citation.jitx/references/architectural-patterns.md). The dominant failure modes are encoded there as worked counter-examples (Bad/Good + rationale); check each one against the code under review.The skill does not modify code. Findings → caller → fix decision → next iteration.
When the code uses a banned pattern (getattr, type(...), _protected_method(), etc.), or when the agent/author proposes a carve-out ("this getattr is OK because…", "this is the boundary call into the framework…"), the reviewer must answer four questions before accepting the carve-out:
If the answer is "outside the owner, copying internals" or "wrapping the banned pattern in a helper to make it look like one boundary call," classify the finding as framework-boundary-bypass (see references/checklist.md) and recommend the subclass-adapter fix.
This step exists because rule text alone wasn't sufficient: in a real review, the AI followed the no-getattr rule literally (one wrapped getattr call) but missed the rule's intent (don't replicate framework internals in design code) and produced a design coupled to a numbering scheme that the reviewer caught.
Same vocabulary as outside-voice-review.md for consistency:
jitx/SKILL.md Don'ts or architectural-patterns.md. Must be fixed before the task can be accepted. Examples: getattr(self, f"..."), module-level loop populating a global dict, design file with _SIGNAL_LAYER_TO_VIA that duplicates the substrate.list[dict] that might be a legitimate parameter-staging pattern, an f"X_{i}" that might be a log message). Each WARNING needs a disposition: fix or accept with rationale: <why>.from __future__ import annotations, named constant used exactly once, suboptimal naming).Combined with the codex outside-voice precedence rule: any CRITICAL or WARNING finding here changes the combined verdict to issues-pending even if codex says clean. Same rule, two same-tier reviewers.
## JITX code review — <scope, e.g., <ns>/circuits/<circuit>.py>
**Reviewer:** jitx-code-review (same-model self-critique)
**Scope:** <list of files reviewed, with revision/commit if relevant>
**Rule sources read:** jitx/SKILL.md, jitx/references/architectural-patterns.md, <subskill SKILL.mds if relevant>
### CRITICAL
- **<pattern tag>** at `<file>:<line>` — <one-line description>. Rule: "<verbatim quote>" (from <source>). Disposition required.
- ...
### WARNING
- **<pattern tag>** at `<file>:<line>` — <one-line description>. <Why this might be the failure mode vs. legitimate use.> Disposition: fix | accept with rationale: <why>.
- ...
### NOTE
- **<pattern tag>** at `<file>:<line>` — <one-line description>.
- ...
### Summary
CRITICAL: <count> | WARNING: <count> | NOTE: <count>
The <pattern tag> is from the checklist (e.g., string-keyed-model, reflection-as-iteration, owner-shaped-data-misplaced, parallel-data-model). Pattern tags are orthogonal to severity — a single pattern can produce CRITICAL or WARNING findings depending on the specific instance.
pyright and ruff check still run as part of the task acceptance block. They catch type / lint issues; this skill catches architectural smells they can't see.jitx build still runs. This skill is purely a code-quality pass.The skill can become ritual if the reviewer agent passes everything as clean without doing the work. Concrete signals the orchestrator should treat as suspicious:
CRITICAL: 0 | WARNING: 0 | NOTE: 0 on a parametric / generator task where the architectural patterns are likely to surface.file:line citations or rule quotes.NOTE when the pattern checklist named CRITICAL-eligible patterns.all accepted, all framework code) on review-required grep-gate hits — each hit needs a per-line rationale.fix/resolved/accepted with no cited evidence — no fix commit or file:line showing the change, and no stated acceptance rationale. "Resolved" with neither is the author-side form of compliance theater (e.g. a reviewer reopening a thread marked resolved with "not sure what the resolution is"). A resolved disposition must point at the diff that resolved it or say why it's accepted as-is.A valid review output should let a reader open the cited file at the cited line and verify the finding in under a minute.
development
This skill should be used when the user asks to author PCB physical layout from code — "draw copper from code", "create an antenna" / "filter copper" / "net tie" / "overlapping copper", build a "custom shape" or board outline with shapely, add a "custom pad shape", "soldermask/paste opening", or "thermal pad with vias", "place vias from code" / "attach a via to a pad", apply "fanout / escape tags" or "direct-connect / thermal-relief" to layout objects, or (advanced) add "control points" and "code-based routes" for escape routing or deskew. Covers shapely shape creation feeding ANY feature, Copper vs OverlappableCopper vs Pour, pad features (Soldermask/Paste/SMDPadConfig/thermal_pad), PortAttachment + explicit placement, layout-intent tags, and the Route / control-point API (RoutePoint / PairInsertion / PairPoint, stable as of JITX 4.2). For stackup, via definitions, routing structures, fence-via rules, and fenced pour outlines use jitx-substrate-modeler; for net wiring, passives, and basic pours use jitx-circuit-builder.
data-ai
Mechanical CAD interface for JITX designs. Use when the user asks to import DXF, EMN, IDF, IDX, or BDF mechanical data; set a board outline from mechanical CAD; export a JITX board to DXF; attach STEP models; export board STEP; or work with mechanical CAD data.
development
Base skill for JITX hardware design workflow. Use for JITX Python projects, PCB design, circuit creation, and build commands. Use when the user asks to "build my JITX design", "set up JITX environment", "create a circuit", "build a complete board", "design a PCB from requirements", or "create a full JITX project". For multi-component designs (3+ components, substrate, circuits), invoke the Project Builder workflow for orchestrated parallel agent execution with quality gates. CRITICAL - If user asks to create/model/generate a component or mentions a part number (NE555, LM1117, RP2040, etc.), immediately invoke jitx-component-modeler subskill. If user asks to create a substrate, stackup, via definitions, or routing structures, invoke jitx-substrate-modeler subskill. If user asks to author physical layout from code — draw copper, antennas, filters, or net-ties; build custom shapes with shapely; add pad/soldermask/paste/thermal-pad features; place vias or routes from code; or apply fanout/escape/direct-connect layout tags — invoke jitx-physical-layout subskill. If user asks to import DXF/EMN/IDF/IDX/BDF mechanical data, set board outline from mechanical, export STEP, add a 3D model, export JITX board XML to DXF, or work with mechanical CAD data, invoke jitx-mechanical subskill.
testing
This skill should be used when the user asks to "create a substrate", "define a stackup", "add via definitions", "set up routing structures", "configure impedance control", "define differential pairs", "set fabrication rules", "ring a shape with fence vias", "fence a pour outline", "fence an antipad", or "model a PCB layer structure". Ask the user which fabrication house they are targeting — if they confirm JLCPCB, predefined substrates from jitxlib.jlcpcb (JLC04161H_1080, JLC04161H_7628, JLC06161H_7628) are available with 4/6-layer FR-4, 50/90/100 ohm routing structures, vias, and fab rules. Otherwise, create a custom substrate. Covers Stackup, Symmetric, Conductor, Dielectric, Via (laser, mechanical, backdrilled, blind, buried, stacked), RoutingStructure, DifferentialRoutingStructure, NeckDown, via fencing along traces, fenced pour outlines (Tag + fence_via rule paired with a Pour + optional same-shape KeepOut — covers antipads, RF cavities, BGA breakouts), geometry, reference planes, and FabricationConstraints.