aeondave/jtag-swd
offensive-hardware/jtag-swd/SKILL.md
Non-destructive JTAG/SWD pin identification, OpenOCD configuration, CPU halting, and runtime memory dumping.
$ install --global
skillsauthnpx skillsauth add aeondave/malskill jtag-swdInstall this skill globally with one command. Works with Claude Code, Cursor, and Windsurf.
Security Scan Results
3 of 9 scanners reported clean
Some scanners were skipped, did not run, or reported a non-clean status. Review each row below.
3
Scanners Passed
9
Scanners in report
Clean
TrivyContainer and dependency vulnerability scanner
95%
Clean
SemgrepStatic code analysis for vulnerabilities
95%
Clean
mcp-scan (Snyk)Model Context Protocol security validation
95%
Skipped
Snyk (dep)Open source security scanning
50%
Skipped
Socket.devSupply chain security analysis
50%
Skipped
VirusTotalMulti-engine malware detection
50%
Skipped
CrowdStrikeAdvanced threat intelligence
50%
Skipped
OSV-ScannerOpen Source Vulnerability database check
50%
Skipped
OWASP Dep-Check
50%
Last scanned: Jun 12, 2026, 3:49 AM8.5s2 files scanned
SKILL.md
- name:
- jtag-swd
- description:
- Non-destructive JTAG/SWD pin identification, OpenOCD configuration, CPU halting, and runtime memory dumping.
jtag-swd
Use when firmware extraction is needed but direct SPI flash reading is physically impossible (BGA chips, eMMC), or live debugging/execution flow control is required.
1. Interface identification
- Standard JTAG:
TCK,TMS,TDI,TDO,nTRST,nSRST,GND,VCC. - ARM SWD: Compact 2-wire alternative (
SWDIO,SWDCLK,GND,VCC). - Use tools like JTAGulator or JTAGenum on unknown pin headers to automatically scan for TDO responses without manual probing.
2. OpenOCD connection
Map the physical interface (e.g., FTDI-based programmer like Olimex or TIAO) and the target MCU architecture.
# Example: Connect to an STM32F4 via an Olimex ARM-USB-OCD-H programmer
openocd -f interface/ftdi/olimex-arm-usb-ocd-h.cfg -f target/stm32f4x.cfg
3. Execution control & dumping
Connect to OpenOCD's telnet control interface (localhost:4444).
> telnet localhost 4444
# Halt the CPU execution cleanly
> halt
# Inspect CPU state and registers
> reg
# Dump specific memory region (e.g., 1MB starting from flash base 0x08000000)
> dump_image firmware.bin 0x08000000 0x100000
# Resume normal execution
> resume
4. Risks & Considerations
- Watchdog Timers: Halting via JTAG may trigger hardware watchdogs, causing abrupt resets.
- Read-out Protection (RDP): Microcontrollers (especially STM32/NRF) often set internal fuses disabling JTAG debug access or flash reads. Bypassing requires chip-specific glitching workflows.
References
- references/stm32-rdp-bypass.md — Load when an STM32 Read-Out Protection (RDP) prevents memory extraction in OpenOCD.
Related Skills
aeondave/unicorn
development
VerifiedTrustedCommunity
Auth/lab ref: Unicorn Engine CPU-only emulation for shellcode, decryptors, custom VM handlers, instruction tracing, memory hooks, and register-level experiments.
11SKILL.mdUpdated Jul 24, 2026
aeondave/renode
development
VerifiedTrustedCommunity
Auth/lab ref: Renode board and SoC simulation for MCU/RTOS firmware, UART/GPIO/peripheral modeling, GDB remote debugging, REPL platforms, and RESC scripts.
11SKILL.mdUpdated Jul 24, 2026
aeondave/qiling
development
VerifiedTrustedCommunity
Auth/lab ref: Qiling OS-layer binary emulation for PE/ELF/Mach-O/UEFI/shellcode with rootfs, syscall/API hooks, filesystem mapping, and runtime patching.
11SKILL.mdUpdated Jul 24, 2026
aeondave/qemu
databases
VerifiedTrustedCommunity
Auth/lab ref: QEMU user-mode and full-system emulation for cross-arch binaries, firmware, kernels, disks, serial consoles, networking, and GDB stubs.
11SKILL.mdUpdated Jul 24, 2026